BOTTOM LINE: India has moved from PowerPoint to poured concrete on packaging and assembly. But “chip manufacturing ready” and “wafer fab ready” are two different claims — and conflating them is where most India semiconductor coverage goes wrong.
What's Actually Working:
That execution speed — cabinet approval to commercial shipment inside 14 months — is genuinely notable. Few emerging semiconductor geographies move that fast on packaging. This is where India's real comparative advantage sits: OSAT is labor- and process-discipline-intensive rather than fundamentally deep-tech-dependent the way front-end wafer fabrication is. It plays to existing strengths — an English-speaking technical workforce, electronics manufacturing muscle built up during the mobile PLI era, and a government machinery that has learned to move fast when it wants results on the ground.
The Wafer Fab Story — Where the Caveats Live:
That node choice is strategic, not a consolation prize. 28nm is the sweet spot for automotive, industrial, and consumer IoT applications — India isn't competing with TSMC's leading-edge nodes, it's building the base layer for what India actually manufactures: cars, phones, industrial equipment. On wafer size, this effectively means India's first fab will run 300mm — the industry-standard wafer for mature-node logic today. Dedicated 200mm capacity, still critical globally for analog, power, and MEMS applications, hasn't been anchored at scale yet in India — a genuine gap rather than a footnote, since 200mm fabs are typically cheaper to stand up and better suited to a first-mover ecosystem still building supplier depth.
Readiness at a Glance:
Layer 1 : OSAT / ATMP (assembly, test, packaging)
Readiness: Investment-grade.
Assessment: Operational, derisking fast — Micron, Kaynes, CG Power, Tata all live or scaling.
Layer 2: Mature-node 300mm wafer fab (28nm+)
Readiness: Credible, unproven
Assessment: Tata–PSMC Dholera in tool-in phase; first silicon late 2026; yields still TBD.
Layer 3: 200mm wafer capacity
Readiness: Early gap
Assessment: No dedicated 200mm anchor at scale yet — a real white space, not a footnote.
Layer 4: Equipment, gas & chemical supply chain
Readiness: Structural risk
Assessment: Being built concurrently with the fab rather than ahead of it.
Layer 5: Design talent
Readiness: Global-Caliber
Assessment: Bengaluru/Chennai/Hyderabad teams did full 2nm tape-out design for Qualcomm.
Layer 6: Fab operations talent
Readiness: Thin, importing
Assessment: Process-engineering bench is shallow; leadership largely recruited from abroad
The Honest Challenges:
Talent — deep in design, shallow in fab operations:
Water, power, and single-site concentration risk:
First silicon in 2026 is not the same as commercial-grade yields. The gap between “wafers came off the line” and “yields are good enough to be commercially competitive” has historically taken new fab entrants longer than initial plans suggested. The government's own framing treats Micron's fab as a future “proof of concept” that would need to succeed before other international players commit to larger investments — an honest admission that this is still being proven, not assumed.
What's Underappreciated — In India's Favor:
The geopolitical tailwind is doing real work that no incentive scheme could buy on its own. US-China decoupling, Taiwan Strait risk, and Hormuz-linked disruption are simultaneously pushing global semiconductor diversification toward India. India doesn't need to out-compete Taiwan on process technology — it needs to be the credible “second source” option, and there is genuine customer pull for that role right now, not just government push. A potential revival of the Adani-Tower Semiconductor fab proposal in Maharashtra, targeting analog and mixed-signal markets, is reportedly under a commercial feasibility refresh — if it lands, it diversifies both the geography and the node-mix beyond Dholera.
THE VERDICT OSAT/ATMP: investment-grade and derisking well. Mature-node (28nm+) 300mm wafer fab: credible but unproven — 18 to 24 months from knowing if it actually works. 200mm-specific capacity and the deep supply-chain layer beneath the fab: still the real gap, and the one least visible in official communications. The government's own target — 1-2% of global semiconductor market share by 2030, up from close to zero today — is itself a tacit admission of how early this remains.
Practical Implications:
- Engage now on the OSAT/packaging layer, where execution risk is largely retired and commercial relationships can be built on operating facilities today.
- Treat the Dholera fab as a real but unproven bet — monitor through 2027 yield data rather than 2026 ribbon-cutting announcements.
- Watch the equipment and materials supply chain layer closely — this is where the next wave of genuine white-space opportunity, and genuine risk, actually sits.
- Track 200mm capacity specifically as a distinct thesis from the 300mm mega-fab narrative — it is underserved and structurally suited to a faster, lower-capex second wave of investment.